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FPGA/SoC 솔루션 FPGA/SoC 솔루션

MFP-VU19P-Q

Virtex UltraScale+ VU19P FPGA 4개 SoC 및 ASIC Rapid Prototyping System

Virtex® UltraScale+™ VU19P FPGA모듈 4개와 Base Board로 구성

XCVU19P-FSVA3824 FPGA 4개 장착

4,800만개의 Asic gate, 1,720 I/O제공

고속 SAMTEC QTH 커넥터 확장

DDR4 So-DIMM(Max 32GB 지원)

SelectMap configuration Config Time 40Sec, SD card

Power/Reset/Config control by USB 원격 다운로더 지원

4 Single Ended Signals or 4 Differential Signals

GTY 48 Lane Connector  / PCie Gen3 8Lanes

개별적으로 조정 가능한 최대 14개의 전압 제공

MFP-Series Daughter Module Compatible

 

 

1. Virtex UltraScale+ (XCVU19P-1FSVA3824)Specification table

 

Device

System Logic Cells (K)

CLB Flip-Flops (K)

CLB LUTs (K)

Max. Dist. RAM (Mb)

Total Block RAM (Mb)

UltraRAM (Mb)

XCVU19P

8,938

8,172

4,086

58.4

75.9

90.0

 

Device

DSP Slices

Peak INT8 DSP (TOP/s)

PCIe Gen3 x16/Gen4 x8

Max. Single-Ended HP I/Os

Max. Single-Ended HD I/Os

GTY 32.75Gb/s Transceivers

XCVU19P

3,840

10.4

8

1,976

96

80

 

2.   MFP-VU19PM Block Diagran

  

  

  

 

3. MFP-VU19PM Specification

l  XCVU19P-FSVA3824-1

      Socket or Chip mount

 

l  IO Connector

      MFP-Series Daughter Module Compatible

      DDR4 So-DIMM : 1ea, Max 32GB

      119Pin Connector x 6

      GTY 80 Lane Connector

      GTY U : 8 x 1, 8 x 1

      GTY L : 16 x 1, 16 x 1

      5 VCCO region

      CU1/2,CU4/5 : 1.8/1.5/1.2V

      CU3L3,CU6L3  : 1.8/1.5/1.2V

      10 GPIO Header

l    Base connection

      Global Clock (8ea)

      LVDS or SE : 4

      SE : 4

      JTAG and RESET, Selectmap Bus

      Base Interconnect

      120pin Connector x 7

      85pin Connector x 2

      10pin GPIO(1.8V)

      GTH 16 Lane Connector x 2

4. MFP-VU19P-Q Base Board Block Diagran

  

  

 

5. MFP-VU19P-Q Base Board Specification

l  Baseboard 4 MFP-VU19PM

l  8 Global Clock

-    LVDS  or SE : 12.5~200MHz  4ea

-   SE : 12.5~200MHz 4ea

l JTAG and Selectmap Configuration

     Config Time 40Sec.(using SD card SelectMap)

      Power/Reset/Config control by USB

l  Interconnection

-      FPGA A and B : 420 ea

-     FPGA C and D : 420 ea

-     FPGA A and C : 360 ea

-    FPGA B and D : 260 ea

      FPGA A and B and C and D : 9ea(IO), 25(SelectMap)

      GTH

      FPGA A and B : 8 Lane

       FPGA A and C : 8 Lane

      FPGA A and D : 8 Lane

      FPGA B and C : 8 Lane

내용5...

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